Embodiments of the invention relate to microprocessors, and more specifically, to a system and method of scheduling bus transactions.
Modern computer systems generally include multiple agents, such as microprocessors, storage devices, display devices, input/output devices and/or other integrated circuits that process data requests. The multiple agents communicate over an external bus. The external bus operates to transfer address, data and control signals between these agents.
In multi-agent systems, the bandwidth of the external bus can define a limit to system performance. Clock speeds within an agent typically are much faster than clock speeds of the external bus. A processor core for example can issue many data requests (e.g., read and write requests) in the time the external bus can execute a single request. Further, an agent must share the external bus with other agents. These factors can introduce unwanted latency to the processing of data requests within an agent.
Microprocessors may process core read requests, prefetch requests and write requests. Core read requests are requests for addressed data to be read to the agent""s processing core. Typically, core read requests identify data for which the agent has an immediate need. Prefetch requests, by contrast, refer to data that is likely to be used by the core in the not-so-distant future. By prefetching the data into the agent prior to the time the core actually issues a read request for it, the data should be available to the core in an internal cache. Write requests typically identify data that is being returned by the agent to system storage. The data may be evicted because the agent is no longer using it and new data is being read to a memory location that the evicted data occupied.